三星电子将在台积电3纳米工艺上为英伟达的定制内存芯片制造核心部件。首尔经济日报周日报道称，此消息来自业界消息人士。这将是两家公司首次合作制造高带宽内存（HBM）。
Samsung Electronics will make a core part of Nvidia’s custom memory chips on TSMC’s 3-nanometre process. The Seoul Economic Daily reported the move on Sunday, citing industry sources. It would be the first time the two have worked together on making high-bandwidth memory (HBM).
该部件是基底芯片，即HBM堆叠底部的逻辑层。迄今为止，三星一直为其所有HBM制造基底芯片及其上的内存芯片。这种做法被称为交钥匙方案。根据报道，三星决定为英伟达改变这一做法。
The part is the base die, the logic layer at the bottom of an HBM stack. Until now, Samsung has made both the base die and the memory dies above it for all of its HBM. That is called a turnkey approach. It has decided to change that for Nvidia, according to the report.
英伟达对NVHBM的需求是其定制HBM，该产品于8月发布。英伟达要求其三家NVHBM供应商在台积电3纳米工艺上制造基底芯片。这些供应商为三星、SK海力士和美光。英伟达还希望将内存芯片标准化为1c，即DRAM技术的第六代。NVHBM采用HBM4E的设计，HBM4E是HBM的第七代。
What Nvidia asked for NVHBM is Nvidia’s custom HBM, unveiled in August. Nvidia has asked all three of its NVHBM suppliers to make the base die on TSMC’s 3nm process. Those suppliers are Samsung, SK Hynix and Micron. Nvidia also wants the memory dies standardised on 1c, the sixth generation of DRAM technology. NVHBM uses the design of HBM4E, the seventh generation of HBM.
首尔经济日报称，原因在于一致性。当供应商采用不同方法时，一种设计难以在所有供应商处实现相同性能。统一工艺也意味着英伟达无需分别验证每家供应商的芯片。三星的器件解决方案部门在内部审查后同意了此举。
The reason is consistency, the newspaper said. When suppliers use different methods, one design is hard to make perform the same way across all of them. A common process also means Nvidia does not have to validate each supplier’s chips separately. Samsung’s Device Solutions division agreed after an internal review.
两家公司四年前曾合作过，当时三星确保其HBM适配台积电的封装工艺。
The two companies worked together four years ago, when Samsung made sure its HBM fitted TSMC’s packaging process.
基底芯片的重要性：NVHBM将内存控制器从GPU移至基底芯片。据首尔经济日报另一篇报道，这为GPU腾出了空间，可容纳更多计算电路。为腾出空间，与其他芯片通信的物理层相比标准HBM缩小了60%。报道称，由此可实现比标准HBM4E高达30%的带宽提升和15%的功耗降低。
Why the base die matters NVHBM moves the memory controller off the GPU and onto the base die. That is according to a second Seoul Economic Daily report. That frees space on the GPU for more computing circuits. To make room, the physical layer that talks to other chips is 60% smaller than in standard HBM. The result is up to 30% more bandwidth and 15% less power than standard HBM4E, the report said.
业界认为台积电3纳米工艺的良率超过90%。而三星代工相当的2纳米工艺SF2的良率约为60%。
The industry puts TSMC’s 3nm yield at more than 90%. That compares with about 60% for Samsung Foundry’s comparable 2nm process, SF2.
UBS 预计明年 HBM 需求约为 615 亿千兆比特，增长 91%。它预计存储芯片制造商的新出货量仅为 546 亿千兆比特。报纸称，这将导致约 10% 的缺口。
A supply gap UBS expects HBM demand of about 61.5 billion gigabits next year, up 91%. It expects new shipments from memory makers of only 54.6 billion gigabits. That leaves a shortfall of about 10%, the newspaper said.
台积电正在台南 18 号厂增设两条 3nm 生产线。量产预计将于 2027 年上半年和 2028 年开始。它还计划在亚利桑那州和日本熊本的第二座厂区增设 3nm 生产线。
TSMC is adding two 3nm lines at Fab 18 in Tainan. Mass production is due to start in the first half of 2027 and of 2028. It also plans 3nm lines at its second plants in Arizona and in Kumamoto, Japan.
三星坚持自身路线 三星将继续采用交钥匙方式生产其标准 HBM4 和 HBM4E，这些产品使用其自研的 4nm 基础晶片。它也将对其他客户（包括 AMD）的定制 HBM 采用同样的方式。此外，它还在测试自身代工业务是否能够在 2nm 工艺下生产 NVHBM 基础晶片。一位行业官员表示，这是为了应对需求可能超过台积电产能的情况所做的准备。
Samsung keeps its own route Samsung will keep the turnkey approach for its standard HBM4 and HBM4E, which use its own 4nm base dies. It will also keep it for custom HBM for other customers, including AMD. It is also testing whether its own foundry could make the NVHBM base die on its 2nm process. That is a hedge in case demand outgrows TSMC’s capacity, an industry official said.